EPLO

 
 

Phase Noise(typical)

eplo PhaseNoise
EPLO is a signal generator utilizing PLL (Phase Locked Loop) technique. It provides pure sine signal within the range from 10MHz to 4400MHz. Output options such as LVDS,CMOS sine wave 90° phase difference two outputs are available for your convenience.Less +10dBm or over +10dBm output level can be also available as an option. High accuracy external reference clock can be used to improve frequency stability.
It is compact size and easy to use. To supply 5V single power supply is only thing you have to do.

SPECIFICATION
Output wave sine wave
Output impedance 50Ω
Output frequency range 10M~4400MHz
Output level +10dBm±2dBm
Spurious level -60dBc
Harmonic spurious -30dBc
Internal clock frequency accuracy ±2.5ppm(10MHz)
Operating temperature range 0 ~ + 50°C
Power supply / current less than +5V±5%, 50mA~350mA
Dimensions W50×D75×H13mm


OPTION


External clock input : 10M~100MHz

External clock input impedance

High impedance (standard) if desired, 50Ω possible

Output : specify 5V TTL, 3.3V TTL or LVDS
Output level : -10~+10dBm
High output level : +10~+20dBm
90 ° degree 2 output
Ċ
eplo.pdf
(211k)
未知的使用者,
2013年11月6日 下午10:13