Phase Noise(typical)

REF10MF is a reference clock module utilizing PLL technique which can generate very low phase noise 100MHz VCXO signal. 10MHz is applied to REF10MF as a reference signal. Once using with our products,PCK3GF-1, it can provide desired clock signals from 50MHz to 3000MHz with the same accuracy of 10MHz reference clock. Other frequency for an external clock frequency will be acceptable if desired as an option.


OutputFrequency 100MHz
Output port 2 ports
Output level 3.3V CMOS
Phase noise(Typical) @3GHz
10Hz offset: -75dBc/Hz
100Hz offset: -109dBc/Hz
1KHz offset: -140dBc/Hz
10KHz offset: -151dBc/Hz
100KHz offset: -157dBc/Hz
1MHz offset: -163dBc/Hz
External reference requirement 10MHz ( Other frequency acceptable as an option)
External reference level >-6dBm~+10dBm sine or square wave
External reference input impedance 1K ohm
Supurious -70dBc or less(except harmonics)
PLL loop band 10Hz
Lock range under external clock mode 10MHz ±25ppm
Frequency adjustment range under internal clock mode 10MHz ±25ppm
Unlock output Lock : High level, Unlock : low level
3.3V CMOS level
Interface (1)Asynchronous serial communication 9600bps,
8 bits, one stop bits, non-parity
3.3V CMOS level
Power supply/Current +3.3V ±5% 100mA max
Dimensions W25.4xD20.32xH7.62mm
Operating Temperature range 0 ~ +60 ° C
Storage temperature range -30 ~ 70 ° C

2013年11月29日 下午10:57
2013年11月6日 下午10:15